In an interface circuit that transmits and receives data between circuit boards, between LSIs (Large Scale Integrated Circuits), between a CPU (Central Processing Unit) and a memory, and so on, a phase adjustment circuit that adjusts the phase of a signal, such as a clock signal, is used.
Conventionally, there is known a technique for suppressing the flow of a shoot-through current during phase adjustment and achieving a reduction of power consumption.
Moreover, in recent years, along with an increase of a clock frequency and the like, there is a need for more accurate phase adjustment. As the phase adjustment circuit for performing a fine phase adjustment, there is known a phase adjustment circuit having a plurality of stages of CMOS (Complementary Metal Oxide Semiconductor) inverters, which adjusts the phase of a clock signal by adjusting the number of inverters to be activated.    Japanese Laid-open Patent Publication No. 2004-129110    Japanese Laid-open Patent Publication No. 2001-44822    “IEEE Journal of Solid-State Circuits”, Vol. 41, No. 5, May 2006, pp. 1051-1061
The phase adjustment circuit for performing the fine phase adjustment as described above has problems in that if a shoot-through current flows during phase adjustment, not only the power consumption increases but also the accuracy of phase adjustment degrades. Therefore, with the related art, it is difficult to perform a high-precision phase adjustment with low power consumption.